// V5.008 verilator  don't support stream operator to pack/unpack unpack array, so use pack/unpack module to replace it.
module pack #(
    parameter DW = 32,
    parameter DP = 4
) (
    input [DW-1:0] din[DP-1:0],
    output [DW*DP-1:0] dout
);
  integer i;
  logic [DW*DP-1:0] out;
  always_comb begin
    for (i = 0; i < DP; i = i + 1) begin
      out[i*DW+:DW] = din[i];
    end
  end
  assign dout = out;

endmodule

module unpack #(
    parameter DW = 32,
    parameter DP = 4
) (
    input [DW*DP-1:0] din,
    output [DW-1:0] dout[DP-1:0]
);
  genvar i;
  generate
    for (i = 0; i < DP; i = i + 1) begin : unpank_logic
      assign dout[i] = din[i*DW+:DW];
    end
  endgenerate

endmodule
